The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a complementary insulated gate field effect transistor (referred to as CIGFET, hereinafter) of LOCOS (Local Oxide of Silicon) construction.
Semiconductor memory devices of LOCOS construction constituted by CIGFETs are well known. In such semiconductor memory circuit devices, a multiplicity of wiring layers are formed on a thick oxide film (referred to as the field oxide film, hereinafter) for isolation between transistors. The threshold voltage of the parasitic metal-insulator-semiconductor field effect transistor (referred to as the parasitic MISFET, hereinafter) formed with the gate constituted by these wiring layers is one of the most critical features which limit the operation voltage of the semiconductor memory circuit device. Namely, if the threshold voltage of the parasitic MISFET is low, it is necessary to use a low power supply voltage. Consequently, the use of the semiconductor device is undesirably limited.
It has been previously proposed, therefore, to form a channel stopper just beneath the field oxide film to increase the threshold voltage of the parasitic MISFET as in, for example, the specification of U.S. Pat. No. 4,110,899. According to the technique disclosed in this Patent for forming the channel stopper, it is possible to partly make use of the mask (Si.sub.3 N.sub.4) for forming the field oxide film. Therefore, the technique disclosed in this prior Patent offers an advantage of higher density of integration than the conventional method for forming a channel stopper in an ordinary planar CMISFET. However, this technique requires steps of treatment with photoresist masks, for selectively forming channel stoppers of different conduction types on the substrate surface and on the well regions. Accordingly, the treatment with photoresist masks in turn requires a highly precise alignment of the masks. For these reasons, the process in accordance with the technique disclosed in the aforementioned Patent is undesirably complicated.